Biography: Tan-Phat Dang received a Bachelor of Science (B.Sc.) degree and a Master of Science (M.S.) degree in Electronics Telecommunications Engineering and Electronics Engineering, awarded by the University of Science, Ho Chi Minh City (HCMUS) in 2018 and 2023, respectively. Presently, he is an active member of the Faculty of Electronics and Telecommunications (FETEL) at HCMUS, Vietnam. His primary focus lies in FPGA-based hardware accelerators.

Research Interests: Hardware accelerator, Cryptography, Video Compression

Teaching: Computer Structure Lab, Connectivity and DAQ for IoT.

Project: 

• Security Enhancement for data sharing based on SoC FPGA. ĐTVT 2022-03.

• Research and development of security systems using accelerators based on the SoC FPGA platform. ĐTVT 2022-04.

• Research and implementation of several hardware accelerators used in modern video compression standards. ĐT-VT 2023-07

• Design an MRF-ME accelerator for H.266/VVC standard. DTVT 2024-01

• Implement FPGA-based ME hardware accelerator in the H.266/VVC video compression standard. T2024-56

• Implement the IC design of ME for the H.266 standard and conduct experiments with a RISC-V CPU on FPGA. DS.C2025-18-15.

Publication: 

1. Nguyen, N. H., Dang, T. P., Bui, T. D., Hoang, T. T., Pham, C. K., & Huynh, H. T., “Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding”, in Computational Science and Its Applications - ICCSA 2024 Workshops. Cham: Springer Nature Switzerland, 2024, pp. 110-121.

2. Nguyen, N. H., Dang, T. P., Tran, T. K., Bui, T. D., Hoang, T. T., & Huynh, H. T., “A configurable 2D integer DCT Hardware Accelerator compatible with H.266 standard based on RISC-V Architecture'”, in 2024 7th International Seminar on Research of Information Technology and Intelligent Systems (ISRITI).

3. Huynh, H. T., Tran, T. K. & Dang, T. P.(2024). Implementing a very high-speed secure hash algorithm 3 accelerator based on PCI-express. International Journal of Reconfigurable and Embedded Systems (IJRES), DOI: 10.11591/ijres.v14.i1.pp1-11

4. Huynh, H. T., Dang, T. P., Tran, T. K., Hoang, T. T., & Pham, C. K. (2024). A multimode SHA-3 accelerator based on RISC-V system. IEICE Electronics Express, 21(11), 20240156-20240156. 

5. T.-P. Dang, T.-K. Tran, T.-T. Hoang, C.-K. Pham, and H.- T. Huynh, A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks, Lecture Notes on Data Engineering and Communications Technologies, 1/1/2023 - 1/1/2023, Ho Chi Minh, Vietnam.

6. T.-P. Dang, T.-K. Tran, T.-T. Hoang, C.-K. Pham, and H.- T. Huynh, The Efficiency of High-performance SHA-3 ĐT-VT 2022-03 97983503154 86 3Accelerator on the System Level, Proceedings - 2023 International Symposium on Electrical and Electronics Engineering, ISEE 2023, 1/1/2023 - 1/1/2023, Ho Chi Minh, Vietnam.

7. H.-T. Huynh, T.-P. Dang, T.-T. Hoang, C.-K. Pham, and T.- K. Tran, An Efficient Cryptographic Accelerators for IoT System Based on Elliptic Curve Digital Signature, Communications in Computer and Information Science, 1/1/2023 - 1/1/2023, Can Tho, Vietnam.

8. T.-K. Tran, T.-P. Dang, T.-T. Hoang, C.-K. Pham, and H.- T. Huynh, Optimizing ECC Implementations Based on SoC-FPGA with Hardware Scheduling and Full Pipeline Multiplier for IoT Platforms, Lecture Notes on Data Engineering and Communications Technologies, 1/1/2023 - 1/1/2023, Ho Chi Minh, Vietnam.

9. T. -K. Tran, T. -P. Dang, T. -T. Bui and H. -T. Huynh, A Reliable Approach to Secure IoT Systems Using Cryptosystems Based on SoC FPGA Platforms, Proceedings - 2021 International Symposium on Electrical and Electronics Engineering, ISEE 2021, 1/1/2021 - 1/1/2021, Ho Chi Minh, Vietnam.

10. H.-T. Huynh, T.-K. Tran, T.-P. Dang, and T.-T. Bui, Security Enhancement for IoT Systems Based on SoC FPGA Platforms, Proceedings - 2020 4th International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SigTelCom 2020, 1/1/2020 - 1/1/2020.